Abstract: In order to minimize the number of through-silicon via (TSV) between different layers in the physical design of three-dimensional integrated circuit (3D IC) and reduce the cost of chip manufacture, a 3D IC partitioning method based on the variable neighborhood search algorithm (VNS) is proposed. Firstly, the approach by utilizing a minimum secant algorithm to partition the two-dimensional circuit into multiple partitions, where the number of partitions matches the required layers. Then, a linear sorting algorithm is used to stack-sort the partitions to find the layer-placement order with the minimum number of long connections. Finally, an improved VNS is applied to move the cells between layers, and a force-oriented mechanism is introduced to reduce the search space of neighborhoods, which further reduces the number of TSV. By testing and analyzing our algorithm on internationally common benchmarks and comparing the results with the best-performing FSA methods available. The experimental results show that the proposed 3D IC partitioning algorithm achieves the best average total number of TSV, with a reduction in solving time by 94% on average compared to the FSA. The algorithm presented in this paper effectively addresses the 3D IC partitioning problem and demonstrates remarkable practical value.