Abstract:
In order to minimize the number of through-silicon vias (TSVs) between different layers in the physical design of three-dimensional integrated circuits (3D ICs) and reduce the cost of chip manufacturing, a 3D IC partitioning method based on the variable neighborhood search (VNS) algorithm is proposed. Firstly, the minimum secant algorithm is utilized to partition a two-dimensional circuit into multiple partitions, where the number of partitions matches the required number of layers. Then, the linear sorting algorithm is used to stack-sort the partitions to determine the optimal layer-placement order with the minimum number of long connections. Finally, an improved VNS algorithm is applied to move the cells between layers, incorporating a force-oriented mechanism to reduce the search space of neighborhoods, which further reduces the number of TSVs. Benchmark tests using internationally recognized datasets are conducted and the proposed method is compared with the currently best-performing FSA method. Experimental results show that the proposed 3D IC partitioning algorithm achieves the best average total number of TSV, with a reduction in computation time by an average of 94% compared to the FSA method. The proposed algorithm effectively addresses the 3D IC partitioning problem and demonstrates remarkable practical value.